Verilog note : installation and simulation

日誌2019-10-05 11:23

作者：Little My Maid 司城杏梨

1. Install Iverilog (append gtkwave)

2. Setting path as C:\iverilog\bin & C:\iverilog\gtkwave\bin

(when editing the path variable , use ; to separate both)

3. Download Notepad++ to be your coding environment

4. Writing verilog needs two files,

one is for setting variable type and constructing circuits,

the other one is setting the binary status and latency

5. After writing your codes, enter the text below on CMD

Compilation: %> iverilog 1.v 2.v

Simulation: %> vvp a.out -lxt2

Waveform viewer: %> gtkwave dump.lx2

6. Next you will see this on the screen

7. Clip your filename and then select the signals

8. Clip Append and Zoom fit, you will see the wave

END

【日誌】品客安格斯厚牛起士堡風味洋芋片

2019-10-05 12:27邊緣的綠頭精：
難打頭...
2019-10-05 13:31Little My Maid 司城杏梨：看波形的東東
2019-10-05 12:50九零年代滑鼠ー‿ー：
專業喔
2019-10-05 13:32Little My Maid 司城杏梨：我每次實習課都忘記怎麼打 = =
2019-10-05 13:32Little My Maid 司城杏梨：然後昨天發呆3節課因為我連加法器是甚麼都不知道...
2019-10-05 13:32福利熊送幸福：
虐我剛剛也在看基本邏輯的波形
2019-10-05 13:35Little My Maid 司城杏梨：我電子學和數位邏輯之前都沒學過... 所以也還在摸 QQ
2019-10-05 13:37私は悲しい。：
https://imgur.com/Al66bLm.jpg
2019-10-05 15:23Little My Maid 司城杏梨：豬突猛進

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